This invention relates to semiconductor devices, and more particularly, to a semiconductor device including a planar junction subject to avalanche breakdown upon a high reverse bias voltage applied thereto.
In a semiconductor device of the type including a planar junction which extends to the surface of the device substrate, it is desirable in many environments to provide a high breakdown voltage of the junction (i.e., the level of reverse bias voltage which results in avalanche breakdown).
A number of approaches have been developed in an attempt to accomplish that goal. In discussing those approaches, reference is made to FIGS. 1-4 showing typical prior art techniques.
Referring to FIG. 1, a typical device 10 of this type is shown, having a substrate 12 including a first region 14 of first (for example P) conductivity type, and a second region 16 of second (for example N) conductivity type. Upon application of a certain level of reverse bias voltage to the device 10, avalanche breakdown will occur. As is well known, the radius of curvature r of the PN junction 18 is very important in determining the breakdown voltage of the device 10. As pointed out in "Physics of Semiconductor Devices", 2nd Edition, authored by S.M. Sze, (1981) at pages 73 and 106-108, the cylindrical and/or spherical regions of the junction 18 have a higher field intensity, so that the level of reverse bias resulting in avalanche breakdown is determined by the radius of curvature of those regions 20. As the radius of curvature of such a cylindrical and/or spherical region 20 is decreased, the breakdown voltage of the device decreases.
In order to increase the radius r, deep diffused junctions 22 (FIG. 2) have been undertaken. While this method has proven effective in increasing the radius r and in turn the breakdown voltage of the device, such an approach requires a long diffusion time and consumes valuable wafer space.
Another well known approach (FIG. 3) for increasing device breakdown voltage is to include a field plate 24 as an extension of contact 26 on region 16b. The field plate 24 extends beyond the junction 28b at the surface 30 of the substrate 12b and over a portion 32 of the substrate 12b, spaced from the portion 32 of the substrate 12b by an oxide layer 34. This has the effect of increasing the dimension of the depletion region along the surface 30 of the substrate 12b when reverse bias voltage is applied to field plate 24 relative to substrate 12b (see dotted line 36 and dimension 38) which in turn increases the breakdown voltage of the device. This approach is described in "Surface Breakdown in Silicon Planar Diodes Equipped with Field Plate", by Conti & Conti, published in Solid-State Electronics, 1972, Volume 15 pages 93-105. While such a method has proven effective in increasing the breakdown voltage of the device, again, similar to the previous method, a large amount of area is taken up, and also, such a method is applicable only over a certain range of resistivities and oxide thicknesses, as field induced breakdown may occur.
Yet another approach for increasing breakdown voltage of such a device is shown in FIG. 4. That approach includes provision of field limiting rings 40 of a conductivity type the same as that of the region 16c. Provision of such rings 40 results in a depletion region which is indicated by the dotted line 42 when reverse bias voltage is applied. Thus, the dimension 44 of the depletion region 42 along the surface 48 of the substrate 12c is increased, in turn resulting in a higher breakdown voltage. This phenomenon is described in "Blocking Capability of Planar Devices with Field Limiting Rings", by Brieger, Gerlach, and Pelka, published in Solid-State Electronics, Volume 26, Number 8, pages 739-745 (1983).
While this system also has proven effective in increasing breakdown voltage, it too has the problem of using up a large surface area.